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[Embeded-SCM Develop] DDSforsinandcos

Description: 用VHDL实现的DDS，可输出正弦、余弦波形。将所有文件放在一个工程文件里，再分别生存模块，按原理图连接及可-using VHDL DDS, output sine, cosine wave. All documents will be placed on a project document, respectively survival module, according to diagram and can link
Platform: | Size: 7168 | Author: 何明均 | Hits:

[Embeded-SCM Develop] fpgapci

Description: 用vhdl编写的pci源代码。花了我2000多元钱买来的，编译通过！-with vhdl pci prepared by the source code. I spent more than 2,000 yuan to buy and compile!
Platform: | Size: 3072 | Author: 王娟 | Hits:

[Software Engineering] DJDPLV_LWB

Description: 利用超高速硬件描述语言(VHDL)在现场可编程逻辑门阵列(FPGA)上编程实现的纯数字式等精度频率计，不但具有较高的测量精度，而且其测量精度不会随着被测信号频率的降低而下降。为了实现对任意信号进行频率测量，在前端输入加整形电路即可。-use ultra-high-speed Hardware Description Language (VHDL) in field programmable logic gate array (FPGA) series The way to achieve such pure digital frequency meter accuracy, not only with higher measurement accuracy, but not its measurement precision frequency signals measured with the decrease. In order to achieve the arbitrary measurement signal frequency, increase input in the front plastic circuit can be.
Platform: | Size: 30720 | Author: 刘刚 | Hits:

[Documents] eb894854-c49f-4ba1-a258-411bc31cf6eb

Description: 介绍了基于FPGA的多功能计程车计价器的电路设计。该设计采用了可编程逻辑器件FPGA的ASIC设计，并基于超高速硬件描述语言VHDL在Xilinx公司的SpartanⅡ系列的2sc200PQ208-5芯片上编程实现了整个系统的控制部分，整个自动控制系统由四个模块构成：秒分频模块、控制模块、计量模块和译码显示模块。该设计不仅仅实现了显示计程车计费的功能，其多功能表现在它可以通过选择键选择显示计程车累计走的总路程和乘客乘载的时间。计时、计程、计费准确可靠，应用于实际当中有较好的实用价值和较高的可行性-introduced FPGA-based multifunctional taxi meter circuit design. The design using programmable logic device FPGA ASIC design, and for the super-high-speed VHDL hardware description language in the company Xilinx Spartan II Series 2 sc 200PQ208-5 chip programming of the control system as a whole, Automatic control the entire system from four modules : a seconds-frequency module, control module, metrology modules and decoding module. The design not only achieved a taxi showed Billing functions, Multifunctional its performance through its keypad revealed taxi taking the cumulative total journey of the passengers took the set time. Program, log, billing is accurate, reliable and practical application of them have good practical value and the higher the feasibility
Platform: | Size: 8192 | Author: 石头 | Hits:

[Other] Altera_FPGA_rumen

Description: Altera的FPGA入门教程，快速使用QuatusII环境开VHDL设计顶层图、状态机，绝对快速上手。-Altera FPGA introductory tutorial, QuatusII rapid use of VHDL design environment for open top map, state machine, absolutely rapid handcuffed.
Platform: | Size: 1629184 | Author: 朱效志 | Hits:

[SCM] MotorControlVHDL

Description: 基于FPGA的步进电机控制电路的VHDL语言-FPGA-based stepper motor control circuit of VHDL
Platform: | Size: 1024 | Author: 邓名成 | Hits:

[VHDL-FPGA-Verilog] fpgalcddriver

Description: 基于FPGA液晶控制器设计与实现，采用VHDL硬件描述语言。-FPGA-based LCD controller design and implementation using VHDL hardware description language.
Platform: | Size: 92160 | Author: 张杰 | Hits:

[Embeded-SCM Develop] vhdlcodes9

Description: FPGA/CPLD集成开发环境ise的使用详解 示例代码9-FPGA/CPLD Integrated Development Environment ise Comments on the use of code examples 9
Platform: | Size: 5120 | Author: bigbibby | Hits:

[VHDL-FPGA-Verilog] VVHDLcodes

Description: 清华大学出版社 VHDL电路设计 一书所有案例源码，省去您敲代码的麻烦，直接仿真吧。-VHDL circuit design a source book all cases, save you the trouble of knocking code, Simulation direct it.
Platform: | Size: 112640 | Author: 潘世雄 | Hits:

[VHDL-FPGA-Verilog] DS18B20+VHDL

Description: 用VHDL语言实现的控制DS18B20构成测温仪表的程序，包含了全部代码，可显示最高精度-with VHDL control DS18B20 constitute Thermometer procedures, contains all the code will show that the most high-precision
Platform: | Size: 818176 | Author: 刘西圣 | Hits:

[VHDL-FPGA-Verilog] Freq_counter

Description: 本代码介绍了使用VHDL开发FPGA的一般流程，最终采用了一种基于FPGA的数字频率的实现方法。该设计采用硬件描述语言VHDL，在软件开发平台ISE上完成，可以在较高速时钟频率（100MHz）下正常工作。该设计的频率计能准确的测量频率在1Hz到100MHz之间的信号。使用ModelSim仿真软件对VHDL程序做了仿真，并完成了综合布局布线，最终下载到芯片Spartan-II上取得良好测试效果。-the code on the FPGA using VHDL development of the general process, finally adopted a FPGA-based digital frequency method. The design using VHDL hardware description language, the software development platform ISE completed, the higher speed clock frequency (100MHz) under normal work. The design of the frequency meter can be accurately measured in a frequency of 100MHz between Hz signal. Use ModelSim VHDL simulation software to do the simulation process, and completed a comprehensive layout cabling, downloaded to the final chip Spartan-II made good on the test results.
Platform: | Size: 515072 | Author: 许的开 | Hits:

[Other] cepinji

Description: 用VHDL 语言描述频率计的设计，其开发均在FPGA中-using VHDL description of the design frequency, the development is in FPGA
Platform: | Size: 1678336 | Author: 侯同 | Hits:

[Software Engineering] pinlvji

Description: 这是一个基于FPGA的频率计和相位计的设计方案-This is an FPGA-based Cymometer and design phase of the program
Platform: | Size: 675840 | Author: zhaoyang | Hits:

[VHDL-FPGA-Verilog] SPI_VHDL

Description: SPI串口的内核实现（vhdl）,可以用qII等软件直接加到FPGA或者CPLD里面.-the SPI Serial Kernel (vhdl) can be used directly qII software foisted CPLD or FPGA inside.
Platform: | Size: 13312 | Author: efly | Hits:

[Software Engineering] VHDL

Description: vhdl语言设计资料，学习FPGA设计的好书籍。-vhdl脫茂脩脭脡猫 录 脝 脳 脢脕脧 拢 卢 脩 搂 脧 掳 FPGA脡猫 录 脝渭脛 潞 脙脢茅 录 庐 隆 拢
Platform: | Size: 1591296 | Author: 闫胜利 | Hits:

[SCM] 9

Description: 本文介绍了两种分频系数为整数或半整数的可控分频器的设计方法。其中之一可以实现50％的奇数分频。利用VHDL语言编程，并用QUARTERS||4.0进行仿真，用 FPGA 芯片实现。 关键词：半整数，可控分频器，VHDL, FPGA -This article describes two kinds of sub-frequency coefficient is an integer or half-integer divider controllable design method. One of them can achieve 50 of the odd-numbered sub-frequency. The use of VHDL language programming, and QUARTERS | | 4.0 simulation, using FPGA chip. Key words: semi-integer, controllable divider, VHDL, FPGA
Platform: | Size: 180224 | Author: 陈金豹 | Hits:

[Program doc] Viterbi

Description: 三篇关于Viterbi FPGA编译码器的优化设计文档： 1、Viterbi译码器的FPGA设计实现与优化.pdf 2、Viterbi译码器的低功耗设计.pdf 3、基于FPGA的高速并行Viterbi译码器的设计与实现.pdf-3 on the Viterbi FPGA optimization codecs design documents: 1, Viterbi decoder FPGA Design Implementation and Optimization. Pdf2, Viterbi decoder, low-power design. Pdf3, high-speed FPGA-based parallel Viterbi decoder Design and Implementation. pdf
Platform: | Size: 451584 | Author: helei_zju | Hits:

[VHDL-FPGA-Verilog] USB_VHDL_CODE

Description: USB接口控制器参考设计VHDL代码,方便开发FPGA人员进行USB的开发，是一个不错的源码。-USB interface controller reference design VHDL code, facilitate the development of FPGA personnel USB development, is a good source.
Platform: | Size: 60416 | Author: hyl | Hits:

[Other] datang(FPGA)

Description: 大唐电信FPGA设计经验.pdf 对初涉及FPGA者来说，无疑是很好的指导。 从开始就让别人的经验成为自己的习惯-Datang Telecom FPGA design experience. Pdf for the beginning of persons involved in FPGA is undoubtedly in good hands. From the beginning the experience of others and become their own habits
Platform: | Size: 967680 | Author: 高 | Hits:

[VHDL-FPGA-Verilog] FPGA_write_sram

Description: FPGA向SRAM中写入数据，VHDL编程-FPGA to the SRAM write data, VHDL programming
Platform: | Size: 262144 | Author: 简 | Hits:
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